1. Field of the Invention
The present invention relates to field-programmable gate arrays, and more particularly, to a method and apparatus for tracking and validating the use of FPGA designs that have been embedded in various integrated circuits.
2. Description of the Related Art
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifinction circuits (or configurable functional blocks) capable of realizing all Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional blocks typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain one or two flip-flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
FPGAs typically included a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Once a specific configuration of an FPGA has been decided upon, it can be configured to perform that one specific function.
The user programmable switches in an FPGA can be implemented in various technologies, such as ONO antifuse, Mxe2x80x94M antifuse, SRAM memory cell, Flash EEPROM memory cell, and EEPROM memory cell. FPGAs that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of an FPGA can be reprogrammed repeatedly. In this scenario, an NMOS transistor is typically used as the switch to either connect or disconnect two selected points (A, B) in the circuit. The NMOS"" source and drain nodes are connected to points A, B respectively, and its gate node is directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, the switch can be turned on or off and thus point A and B are either connected or disconnected. Thus, the ability to program these switches provides for a very flexible device.
FPGAs can store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory CM determines the cells"" function and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.
In general, an FPGA is one type of programmable logic device (PLD), i.e., a device that contains many gates or other general-purpose cells whose interconnections can be configured or xe2x80x9cprogrammedxe2x80x9d to implement any desired combinational or sequential function. As its name implies, an FPGA is xe2x80x9cfield-programmablexe2x80x9d, meaning that the device is generally programmed by designers or end users xe2x80x9cin the fieldxe2x80x9d via small, low-cost programming units. This is in contrast to mask programmable devices which require special steps in the IC chip-manufacturing process. A field-programming unit typically uses design software to program the FPGA. The design software translates a specific configuration of the programmable switches desired by the end-user into a bit stream which is fed into the FPGA. The bit stream creates the pattern of the data in the configuration memory CM that determines whether,each memory cell stores a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. The stored bit in each CM controls whether its associated transistor switch is turned on or off.
Designers of FPGAs (as well as other PLDs) often provide their circuit designs to IC manufacturers who embed the FPGA designs into larger ICs. An example of such a larger IC is a system on a chip (SOC) that includes the embedded FPGA as well as several other components. The several other components may include, for example, a microprocessor, memory, arithmetic logic unit (ALU), state machine, etc. In this scenario the embedded FPGA is only a small part of the whole SOC.
The FPGA designer typically licenses the manufacturer of the larger IC to use the FPGA design in certain products, e.g., certain SOC chips. Use of the FPGA design in any other products is a violation of the license agreement. It is difficult, however, for the FPGA designer to track the use of its design in unlicensed products due to the microscopic design being concealed in the IC. Thus, there is a need for a way for designers of FPGAs (and other PLDs) to track and validate the use of their designs that have been embedded in various ICs.
The present invention provides a method of configuring a field-programmable gate array (FPGA). The method includes storing configuration data used for configuring programmable interconnections among a plurality of X and Y signal lines in memory cells in the FPGA used for implementing the programmable interconnections; and storing bits of data that form at least a portion of a validation number in memory cells in the FPGA that are not used for implementing the programmable interconnections.
The present invention also provides an apparatus including an FPGA. The FPGA includes a plurality of X signal lines, a plurality of Y signal lines, and a plurality of memory cells. A first set of the memory cells are used to implement programmable interconnections between the X and Y signal lines, and a second set of the memory cells are not used to implement programmable interconnections between the X and Y signal lines. Configuration data that is used to implement a specific configuration of the programmable interconnections between the X and Y signal lines is stored in the first set of memory cells, and at least a portion of a validation number is stored in at least some of the second set of memory cells.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.